Header:
iterations: 0000012c
timeout: 30s
io_out_gate: 04044750
io_out_byte: 040411d4 04041244 040412b4 04041324 04041394 04041404 04041474 040414e4
io_in_gate: 04044734
io_in_byte: 04040754 040407c4 04040834 040408a4 04040914 04040984 040409f4 04040a64
memtest: 040446fc
exit_pin: 04044718
flag_pin: 0404476c
memaddr: 04044830 0404484c 04044868 04044884 040448a0
membyte: 04041538 04041554 04041570 0404158c 040415a8 040415c4 040415e0 040415fc
mem: 04 c7 26 c4 08 07 46 44 3b 08 c7 be 1b a1 f1 29 39 51 a6 4a 08 07 c6 ba 67 de ba b7 f6 ba 60 00

# 8-bit constants @ 04040000
# Immediate constants file IMM
const BYTE_3F[7:0] = 0x3f;
const BYTE_D5[7:0] = 0xd5;
const BYTE_54[7:0] = 0x54;
const BYTE_00[7:0] = 0x0;

# 1-bit constants @ 04040380
const TRUE = 1;
const FALSE = 0;

# Various self-contained asserts @ 040403b8
# These asserts/regs have to pass and won't be used elsewhere.
# We can ignore.

# Latched Register File @ 04040658
# Control signals for latched registers @ 04040658
LatchedRegisterFile R
- 4 8-bit registers: R0, R1, R2, R3
- R0 is mapped to IO_IN_BYTE[7:0]
- R3 is mapped to IO_OUT_BYTE[7:0]
- Register select is given by MEM_B[5:4]
- Set control signal given by MEM_B[0]
- Value to write given by ALU_out[7:0] (begins @ 04043ec8)

# MEM bytes @ 04041538
# MEM is initialized to 0?
reg MEM_B[7:0] <- MEM[MEM_ADDR[7:0]]

# Instruction Decode @ 04041618
sel1 @ 04041618 = MEM_B[0] ? MEM_B[1]

ins_check = sel1 ? MEM_B[2]
io_in = sel1 ? MEM_B[3]
io_out = sel1 ? MEM_B[4]
flag = sel1 ? MEM_B[5]
memtest = sel1 ? MEM_B[6]
exit = sel1 ? MEM_B[7]

sel2 @ 00416dc = MEM_b[0] ? MEM_B[1]
...

sel2 @ 040416dc = MEM_B[0] ? MEM_B[1]

# Selecting first operand from reg file (?) @ 040416f8
# Select with MEM_B[5:4]
ALU_in0[7:0] = R[MEM_B[5:4]]

# Reading second operand from reg file @ 04041d88
# Select with MEM_B[7:6]
ALU_in1_reg[7:0] = R[MEM_B[7:6]]

# Selecting first register from immediate file (?) @ 040416f8
# Select with MEM_B[5:4]
ALU_in1_imm[7:0] = IMM[MEM_B[7:6]]

# 2-1 mux to select ALU_in1_reg or ALU_in1_imm
# Select on MEM_B[1] (0 is reg, 1 is imm)
ALU_in1 = (MEM_B[1] ? ALU_in1_imm : ALU_in1_reg)

# ALU_0023a378 @ 04042d48
# ALU implementation
ALU:
- Inputs ALU_in0[7:0] @ 04041b20, ALU_in1[7:0] @ 04042ae0
- Control ALU_op[1:0] @ MEM_B[3:2]
  - ALU_op[1:0] = 00b: ALU_in0[7:0] <<< 5
  - ALU_op[1:0] = 01b: ALU_in0[7:0] ^ ALU_in1[7:0]
  - ALU_op[1:0] = 10b: ALU_in0[7:0] + ALU_in1[7:0]
  - ALU_op[1:0] = 11b: ALU_in0[7:0] & ALU_in1[7:0]
- Outputs:
  - ALU_out[7:0] @ 04043ec8
  - ALU_UF (Unsigned overflow) @ 04043af4
  - ALU_OF (Signed/Unsigned overflow) @ 04043e74
  - ALU_ZF (Zero flag) @ 040441d8

# ZF Latch Register @ 4044210
# Initialized to 0
ZF.Set = MEM_B[0]
ZF.In = ALU_ZF

IP_sel = (MEM_B[2] ? ZF) ? sel2
IP_next[4:0] @ 040442f0 = IP[4:0] + 1
IP[4:0] <- (IP_sel ? MEM_B[7:3] : IP_next[4:0])

# Pins
MEMTEST = memtest
EXIT = exit
IO_IN = io_in
IO_OUT = io_out
FLAG = flag

# INS_CHECK latch register
# Initialized to 0
INS_CHECK.Set = ins_check
INS_CHECK.In = 1

# No idea
ASSERT(INS_CHECK ? IP_next[1]);

MEMADDR = IP